Processor and operating method for a homogeneous dual computing system
US12222868B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 15, 2023 |
| Grant date | Feb 11, 2025 |
| Priority date | — |
| Expiry date | Oct 13, 2043 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor for building a homogeneous dual computing system is shown. The processor has a trusted core, a normal core, and a shared cache. The trusted core has an access right to an isolated storage space of a system memory. The normal core is homogeneous with the trusted core, and is prohibited from accessing the isolated storage space. In response to a cache flush instruction issued by the normal core, the trusted core initiates and executes a second cache write-back instruction that is different from the first cache write-back instruction. According to the second cache write-back instruction, isolated data associated with the isolated storage space and cached in the shared cache is written back to the isolated storage space before being flushed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.