Combination boot for an integrated circuit
US12223052B1 · kind B1 · utility
0Cited by
9References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 15, 2022 |
| Grant date | Feb 11, 2025 |
| Priority date | — |
| Expiry date | Aug 29, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F21/76
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A boot process for a computing device, such as integrated circuit, includes security features that are inaccessible during certain operation modes. An image including permission to access those security features is received during the boot process and may be verified using one or more keys. In operation, access to the security features is permitted during the operation modes after the image is verified. Such an approach enables a boot process to permit access to certain features after receipt and verification of different images.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.