Hardware-based security authentication
US12223101B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 5, 2023 |
| Grant date | Feb 11, 2025 |
| Priority date | — |
| Expiry date | Oct 5, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/7807
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system includes a multiplexer, an input/output (I/O) pin, a logic circuit, and a control register. The multiplexer has multiple inputs, an output, and a selection input. The logic circuit is coupled between the multiplexer and the I/O pin. The logic circuit has a first input. The control register includes first and second bit fields corresponding to the I/O pin. The first bit field is coupled to the selection input of the multiplexer, and the second bit field is coupled to the first input of the logic circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.