Packaging method and package structure
US12224221B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 13, 2022 |
| Grant date | Feb 11, 2025 |
| Priority date | — |
| Expiry date | Sep 22, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/37001
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A packaging method and a package structure are provided. The packaging method includes the following steps. Firstly, a plurality of chips are disposed on a carrying surface of a carrying board for chip redistribution. Each of the chips includes a first side connected to the carrying surface and a second side opposite to the first side, and the second side is provided with at least one chip connecting member. Next, a base structure is provided. The base structure has a bonding surface provided with a plurality of predetermined areas for bonding the chips respectively, and each of the predetermined regions has at least one electrically connecting structure formed therein. Lastly, an encapsulating material is applied to integrate the base structure, the chips, and the carrying board into a unitary structure under specific hot pressing conditions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.