Patent · US Active

Symmetric dual-sided MOS IC

US12224286B2 · kind B2 · utility

0Cited by

5References

26Claims

0Family size

Assignee

QUALCOMM Incorporated · US

Inventors

Ravi Pramod Kumar VEDULA · San Diego, US
Vikram Sekar · San Diego, US

Key dates

Filing date	Sep 22, 2021
Grant date	Feb 11, 2025
Priority date	—
Expiry date	Aug 17, 2043

Classification

Technology area (CPC H)Electricity
CPC primaryH01L23/66
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A dual-sided MOS IC includes an isolation layer and a MOS transistor. The isolation layer separates the MOS IC into a MOS IC frontside and a MOS IC backside. The MOS transistor is on both the MOS IC frontside and the MOS IC backside. The MOS transistor includes MOS gates, a first source connection in a first subsection of the MOS IC frontside, and a second source connection in a second subsection of the MOS IC backside. The first and second source connections are electrically coupled together through a first front-to-backside connection extending through the isolation layer. The MOS transistor further includes a first drain connection in the first subsection of the MOS IC backside, and a second drain connection in the second subsection of the MOS IC frontside. The first and second drain connections are electrically coupled together through a second front-to-backside connection extending through the isolation layer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.