Size-controllable multi-stack semiconductor device and method of manufacturing the same
US12224314B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Aug 13, 2021 |
| Grant date | Feb 11, 2025 |
| Priority date | — |
| Expiry date | Jul 28, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/85
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A multi-stack semiconductor device includes: a substrate; and a plurality of multi-stack transistor structures arranged on the substrate in a channel width direction, wherein the multi-stack transistor structure include at least one lower transistor structure and at least one upper transistor structure stacked above the lower transistor structure, wherein the lower and upper transistor structures include at least one channel layer as a current channel, wherein the lower transistor structures of at least two multi-stack transistor structures have different channel-layer widths.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.