Heterojunction semiconductor device with low on-resistance
US12224340B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Dec 19, 2019 |
| Grant date | Feb 11, 2025 |
| Priority date | — |
| Expiry date | Aug 12, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/343
Abstract
A heterojunction semiconductor device with a low on-resistance includes a metal drain electrode, a substrate, and a buffer layer. A current blocking layer is arranged in the buffer layer, a gate structure is arranged on the buffer layer, and the gate structure comprises a metal gate electrode, GaN pillars and AlGaN layers, wherein a metal source electrode is arranged above the metal gate electrode; and the current blocking layer comprises multiple levels of current blocking layers, the centers of symmetry of the layers are collinear, and annular inner openings of the current blocking layers at all levels gradually become smaller from top to bottom. The AlGaN layers and the GaN pillars are distributed in a honeycomb above the buffer layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.