Self-aligned gate endcap (SAGE) architectures with vertical sidewalls
US12224349B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 7, 2020 |
| Grant date | Feb 11, 2025 |
| Priority date | — |
| Expiry date | Aug 19, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02576
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Self-aligned gate endcap (SAGE) architectures with vertical sidewalls, and methods of fabricating self-aligned gate endcap (SAGE) architectures with vertical sidewalls, are described. In an example, an integrated circuit structure includes a semiconductor fin having sidewalls along a length of the semiconductor fin, each sidewall tapering outwardly from a top of the semiconductor fin toward a bottom of the semiconductor fin. A gate endcap isolation structure is spaced apart from the semiconductor fin and has a length parallel with the length of the semiconductor fin. The gate endcap isolation structure has a substantially vertical sidewall laterally facing one of the outwardly tapering sidewalls of the semiconductor fin.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.