Semiconductor transistor device including multiple channel layers with different materials
US12224357B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 26, 2022 |
| Grant date | Feb 11, 2025 |
| Priority date | — |
| Expiry date | Sep 14, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/251
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A semiconductor device includes a first active region, a second active region spaced apart from the first active region, a plurality of first channel layers disposed on the first active region, and a second channel layer disposed on the second active region. The semiconductor device further includes a first gate structure intersecting the first active region and the first channel layers, a second gate structure intersecting the second active region and the second channel layer, a first source/drain region disposed on the first active region and contacting the plurality of first channel layers, and a second source/drain region and contacting the second channel layer. The plurality of first channel layers includes a first uppermost channel layer and first lower channel layers disposed below the first uppermost channel layer, and the first uppermost channel layer includes a material that is different from a material included in the first lower channel layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.