Error correction method, error correction circuit and electronic device applying the same
US12224768B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 3, 2023 |
| Grant date | Feb 11, 2025 |
| Priority date | — |
| Expiry date | Jul 3, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/6597
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An error correction method comprises: when a decoder determines that an input analog code is at a forbidden state, setting a digital binary code as a first predetermined code and inputting the digital binary code to an ECC engine; determining whether the digital binary code has no error or two errors; when the digital binary code has no error, outputting the digital binary code after ECC by the ECC engine; when the digital binary code has two errors, resetting the digital binary code as a second predetermined code and inputting the digital binary code to the ECC engine for ECC; and when the decoder determines that the input analog code is not at the forbidden state, decoding the input analog code into the digital binary code and inputting the digital binary code to the ECC engine for ECC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.