Low headroom cascode bias circuit for cascode current mirrors
US12228956B2 · kind B2 · utility
0Cited by
2References
14Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 7, 2022 |
| Grant date | Feb 18, 2025 |
| Priority date | — |
| Expiry date | Jun 29, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F3/262
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A cascode bias circuit biases a gate of a cascode transistor in a cascode current mirror. The cascode bias circuit includes a first transistor configured to conduct a first current and includes a second transistor configured to conduct a second current. The first and second transistors couple to a third transistor configured to conduct a sum of the first current and the second current. A gate of the first transistor couples to a gate of the cascode transistor to bias the cascode transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.