Apparatus and method for testing high-speed low-latency interconnect interface (HLII) for silicon interposer
US12229029B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 5, 2023 |
| Grant date | Feb 18, 2025 |
| Priority date | — |
| Expiry date | Oct 1, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4282
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and a method for testing a multi-channel high-speed low-latency interconnect interface (HLII) for a silicon interposer are provided. The apparatus includes: a standard test port configured to exchange a test instruction; an asynchronous bypass port configured to directly access an input/output (I/O) port of a channel of a physical layer of the interconnection interface; a built-in self-test (BIST) engine configured to implement inter-level loopback testing and data verification; a redundant data channel configured to repair a damaged data channel; and a delay chain testing circuit configured to test a function and linearity of a delay chain. The apparatus embeds test and repair logic into the physical layer and a link layer, achieving internal test control without any external controller. In this way, a sample can be tested and quickly screened to ensure its performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.