Devices and methods to secure a system on a chip
US12229253B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jun 7, 2021 |
| Grant date | Feb 18, 2025 |
| Priority date | — |
| Expiry date | Feb 7, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2221/034
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system on a chip comprising a set of one-time programmable memory elements that comprises a first valid configuration; a second valid configuration; and a plurality of invalid configurations. The system on a chip also comprises a programming indicator initially comprising a first value and configured to be permanently set to a second value. The system on a chip further comprises a decoder circuit in communication with the set of one-time programmable memory elements to determine whether the set of one-time programmable memory elements is in the first valid configuration, the second valid configuration, or any one of the plurality of invalid configurations. The decoder circuit generates a threat-detection signal when the set of one-time programmable memory elements is in any of the plurality of invalid configurations when the programming indicator is permanently set to the second value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.