Dynamic buffer for storage system
US12229437B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 3, 2022 |
| Grant date | Feb 18, 2025 |
| Priority date | — |
| Expiry date | Jan 9, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/81
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A storage system has NVRAM (nonvolatile random-access memory), storage memory that includes SLC (single level cell) flash memory and QLC (quad level cell) flash memory, and a processor. The processor performs a method that includes determining that a size of a buffer of a storage system should be adjusted. The storage system comprises a non-volatile random-access memory (NVRAM), single level cell (SLC) flash memory, and quad level cell (QLC) flash memory. The buffer of the storage system comprises one or more of the NVRAM and a portion of the SLC flash memory. The method also includes adjusting the size of the buffer of the storage system to a first size.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.