Semiconductor memory device
US12229450B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 30, 2023 |
| Grant date | Feb 18, 2025 |
| Priority date | — |
| Expiry date | Nov 30, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/107
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device comprises: a first pad receiving a first signal; a second pad receiving a second signal; a first memory cell array; a first sense amplifier connected to the first memory cell array; a first data register connected to the first sense amplifier and configured to store user data read from the first memory cell array; and a control circuit configured to execute an operation targeting the first memory cell array. The first memory cell array comprises a plurality of first memory strings. The first memory strings each comprise a plurality of first memory cell transistors. In a first mode of this semiconductor memory device, a command set instructing the operation is inputted via the first pad. In a second mode of this semiconductor memory device, the command set is inputted via the second pad.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.