Facilitating per-CPU reference counting for multi-core systems with a long-lived reference
US12229559B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 19, 2021 |
| Grant date | Feb 18, 2025 |
| Priority date | — |
| Expiry date | Jun 14, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/526
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Facilitating per-CPU reference counting for multi-core systems with a long-lived reference is provided herein. A system includes a processor and a memory that stores executable instructions that, when executed by the processor, facilitate performance of operations. The operations include determining a first quantity of releases associated with an object in a data structure of the system and determining a second quantity of acquisitions associated with the object. The first quantity of releases can be distributed among respective first counters of processing elements of a group of processing elements. The second quantity of acquisitions can be distributed among respective second counters of the processing elements of the group of processing elements. Further, the operations can include, based on the second quantity of acquisitions and the first quantity of releases being determined to be a same value, implementing a removal of the object from the data structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.