Optimal calibration of gates in a quantum computing system
US12229603B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Nov 19, 2021 |
| Grant date | Feb 18, 2025 |
| Priority date | — |
| Expiry date | Sep 14, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N10/40
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of performing a quantum computation process includes mapping logical qubits to physical qubits of a quantum processor so that quantum circuits are executable using the physical qubits of the quantum processor and a total infidelity of the plurality of quantum circuits is minimized, wherein each of the physical qubits comprise a trapped ion, and each of the plurality of quantum circuits comprises single-qubit gates and two-qubit gates within the plurality of the logical qubits, calibrating two-qubit gates within a first plurality of pairs of physical qubits, such that infidelity of the two-qubit gates within the first plurality of pairs of physical qubit is lowered, executing the plurality of quantum circuits on the quantum processor, by applying laser pulses that each cause a single-qubit gate operation and a two-qubit gate operation in each of the plurality of quantum circuits on the plurality of physical qubits, measuring population of qubit states of the physical qubits in the quantum processor, and outputting the measured population of qubit states of the physical qubits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.