Display panel applied to large size or high pixel density tiling display
US12230170B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2021 |
| Grant date | Feb 18, 2025 |
| Priority date | — |
| Expiry date | May 19, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10H29/142
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A display panel including a bottom plate, a plurality of display modules, and a plurality of connection pixel packages is provided. The display modules are tiled in an array arrangement on the bottom plate. Each of the display modules includes a circuit substrate and a plurality of display pixels. The circuit substrate includes a plurality of connection electrodes. The display pixels are disposed on the circuit substrate and at least one of the display pixels has at least one second pixel unit. Each of the connection pixel packages includes at least one first pixel unit. The connection pixel packages are disposed on the connection electrodes of the adjacent circuit substrates to connect the display modules. A light emitting surface of the at least one first pixel unit and a light emitting surface of the at least one second pixel unit are coplanar.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.