Control method, semiconductor memory, and electronic device
US12230348B2 · kind B2 · utility
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3References
22Claims
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Key dates
| Filing date | Jan 17, 2023 |
| Grant date | Feb 18, 2025 |
| Priority date | — |
| Expiry date | Jul 14, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/36
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present disclosure provide a control method, a semiconductor memory, and an electronic device. When the semiconductor memory is in a preset test mode, a first Model Register (MR) and a second MR related to a Data Pin (DQ) are allowed to directly define the impedance of a Data Mask Pin (DM). The DM does not need to add definition of an output driver state and a related control circuit for the preset test mode to ensure that the preset test mode is adapted to the DM. The impedance of the DM may be tested in the preset test mode to avoid circuit processing errors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.