Acceleration of in-memory-compute arrays
US12230361B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 3, 2023 |
| Grant date | Feb 18, 2025 |
| Priority date | — |
| Expiry date | Jul 3, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/82
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus includes an in-memory compute circuit that includes a memory circuit configured to generate a set of products by combining received input values with respective weight values stored in rows of the memory circuit, and to combine the set of products to generate an accumulated output value. The in-memory compute circuit may further include a control circuit and a plurality of routing circuits, including a first routing circuit coupled to a first set of rows of the memory circuit. The control circuit may be configured to cause the first routing circuit to route groups of input values to different ones of the first set of rows over a plurality of clock cycles, and the memory circuit to generate, on a clock cycle following the plurality of clock cycles, a particular accumulated output value that is computed based on the routed groups of input values.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.