Method for manufacturing electronic chips
US12230602B2 · kind B2 · utility
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12References
20Claims
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Assignee
Inventors
Key dates
| Filing date | Jul 8, 2022 |
| Grant date | Feb 18, 2025 |
| Priority date | — |
| Expiry date | Sep 8, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/94
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing electronic chips includes depositing, on a side of an upper face of a semiconductor substrate, in and on which a plurality of integrated circuits has been formed, a protective resin. The method includes forming, in the protective resin, at least one cavity per integrated circuit, in contact with an upper face of the integrated circuit. Metal connection pillars are formed by filling the cavities with metal. The integrated circuits are separated into individual chips by cutting the protective resin along cut lines extending between the metal connection pillars.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.