Multi-bridge channel field effect transistor with multiple inner spacers
US12230685B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 31, 2022 |
| Grant date | Feb 18, 2025 |
| Priority date | — |
| Expiry date | Jun 8, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/83
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A semiconductor device includes active fins extending in a first direction on a substrate; an isolation insulating layer covering a portion of side surfaces of the active fins; channel layers stacked vertically and spaced apart on the active fins; a gate pattern in a second direction across the active fins and the channel layers; and spacer layers across the active fins in the second direction on both sides of the gate pattern. At least one spacer layer extends downwardly along a side surface of the gate pattern such that a lower surface thereof contacts the isolation insulating layer. The lower surface of the spacer layer is higher than a level of upper surfaces of the active fins. The gate pattern has a lower surface contacting the isolation insulating layer. The lower surface of the gate pattern is lower than a level of the upper surfaces of the active fins.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.