Error amplifier circuit
US12231096B2 · kind B2 · utility
0Cited by
3References
5Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 1, 2022 |
| Grant date | Feb 18, 2025 |
| Priority date | — |
| Expiry date | Sep 21, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/351
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An error amplifier circuit includes: a plurality of error amplifiers, each of which obtains an output for an error between two input signals; and a multiplexer, which selects or deselects the outputs of the plurality of error amplifiers and outputs the selected output of the error amplifier as a control signal for a circuit to be controlled. Regarding the multiplexer, in an error amplifier which is one of the plurality of error amplifiers and of which the output is not selected, a delay element arranged in an input path of the one error amplifier is short-circuited to widen the bandwidth of the error amplifier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.