Semiconductor device and chip singulation method
US12232337B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 1, 2021 |
| Grant date | Feb 18, 2025 |
| Priority date | — |
| Expiry date | May 16, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/668
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device that is a chip-size-package-type semiconductor device that is facedown mountable includes: a semiconductor layer including a semiconductor substrate and a low-concentration impurity layer in contact with an upper surface of the semiconductor substrate; a metal layer having a thickness of at least 10 μm; a first vertical MOS transistor in the semiconductor layer; and a second vertical MOS transistor in the semiconductor layer. A side surface of the metal layer includes roughness forming vertical stripes in a direction perpendicular to the metal layer, and has a maximum height of profile greater than 1.0 μm. In a plan view of the semiconductor device, an area occupancy of a formation containing metal in the metal layer is at most 5% in a 10-μm square region located at least 13 μm inward from an outer edge of the semiconductor device, within an upper surface of the semiconductor device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.