Memory device and scheduling method thereof
US12236098B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 24, 2023 |
| Grant date | Feb 25, 2025 |
| Priority date | — |
| Expiry date | Jun 1, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0679
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory includes: a request register configured to receive a first signal including a requester identifier using a first protocol from a host and configured to output a first priority corresponding to the requester identifier; a checker module configured to receive a second signal including a command and a request type from the host and using a second protocol that is different than the first protocol, where the checker module is configured to receive the first priority from the request register, and where the checker module is configured to determine a second priority of the command based on the first priority and the request type; a command generator configured to generate an internal command for memory operation based on the command; and a memory controller configured to schedule the internal command in a command queue based on the second priority.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.