Accelerator module and computing system including the same
US12236099B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 25, 2023 |
| Grant date | Feb 25, 2025 |
| Priority date | — |
| Expiry date | Nov 3, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/5061
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An accelerator module includes a plurality of memories and a controller. The controller includes a plurality of memory controllers, a plurality of processing units, and a managing circuit. The plurality of memory controllers and the plurality of memories form a plurality of memory sub-channels. The plurality of processing units perform computational operations on a plurality of data stored in or read from the plurality of memories. The managing circuit redistributes tasks performed by the plurality of processing units or changes connections between the plurality of memory controllers and the plurality of processing units in response to a first memory sub-channel and a first processing unit being in a heavy-workload state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.