Processor, signal adjustment method and computer system
US12236108B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 26, 2023 |
| Grant date | Feb 25, 2025 |
| Priority date | — |
| Expiry date | May 7, 2043 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor, a signal adjustment method, and a computer system including the processor are provided, pertaining to the field of computer technologies. The processor includes a memory controller. The memory controller includes a memory physical interface and a first processor core, and the first processor core is connected to the memory physical interface. After the computer system is started and during a running process of the computer system, the first processor core is configured to adjust a timing relationship between a target signal of the memory physical interface and a synchronization signal of the target signal. According to this application, timing alignment can be ensured between the target signal and the synchronization signal, thereby improving correctness of sampling performed on the target signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.