Systems and methods for selectively controlling programming operations of a memory system comprising a plurality of super blocks
US12236116B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 19, 2022 |
| Grant date | Feb 25, 2025 |
| Priority date | — |
| Expiry date | Sep 12, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0679
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system includes a memory controller and a memory device including a plurality of dies, each die including a plurality of blocks. A plurality of commands are configured to control the memory device in units of super blocks. During a first time interval, a first erase operation is performed on a first-first block among the first-first block to a first-Mth block, and a first program operation is performed on a second-first block to a second-Mth block, based on the first commands. During a second time interval, a second erase operation is performed on a first-second block among the first-first block to the first-Mth block, and a second program operation is performed on the first-first block and one or more blocks among the second-first block to the second-Mth block, based on the second commands.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.