Memory circuit and memory
US12236141B2 · kind B2 · utility
0Cited by
3References
15Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 6, 2022 |
| Grant date | Feb 25, 2025 |
| Priority date | — |
| Expiry date | Mar 15, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4097
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuit at least includes a plurality of memory banks, where each of the memory banks includes a first memory sub-bank, a second memory sub-bank and a third memory sub-bank sequentially arranged, the second memory sub-bank including a first memory section and a second memory section, the first memory sub-bank and the second memory section being configured to store upper bytes, and the first memory section and the third memory sub-bank being configured to store lower bytes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.