Large integer multiplication enhancements for graphics environment
US12236238B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 25, 2021 |
| Grant date | Feb 25, 2025 |
| Priority date | — |
| Expiry date | Jun 2, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/38885
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus to facilitate large integer multiplication enhancements in a graphics environment is disclosed. The apparatus includes a processor comprising processing resources, the processing resources comprising multiplier circuitry to: receive operands for a multiplication operation, wherein the multiplication operation is part of a chain of multiplication operations for a large integer multiplication; and issue a multiply and add (MAD) instruction for the multiplication operation utilizing at least one of a double precision multiplier or a 48 bit output, wherein the MAD instruction to generate an output in a single clock cycle of the processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.