Memory device performing refresh operation and method of operating the same
US12236991B1 · kind B1 · utility
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11References
20Claims
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Key dates
| Filing date | Mar 22, 2023 |
| Grant date | Feb 25, 2025 |
| Priority date | — |
| Expiry date | Mar 22, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/70
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a memory cell array, an address manager and a refresh controller. The memory cell array includes a plurality of memory cells coupled to a plurality of word-lines. The address manager samples access addresses provided from a memory controller to generate sampling addresses and determines a capture address from among the access addresses, based on a time interval between refresh commands from the memory controller. The refresh controller refreshes target memory cells from among the plurality of memory cells based on one of a maximum access address from among the sampling address and the captured address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.