Memory device and refresh method thereof
US12236996B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 14, 2023 |
| Grant date | Feb 25, 2025 |
| Priority date | — |
| Expiry date | Aug 21, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device may include counters respectively corresponding to rows and each configured to count a number of accesses to a corresponding row, a refresh control circuit, a queue, and first flags respectively corresponding to the rows. The refresh control circuit may change a second flag set in a refresh period every refresh period, and determine whether to put an incoming row address into the queue based on a count value of a counter corresponding to a target row indicated by the incoming row address among the counters, a first flag value of a first flag corresponding to the target row among the first flags, and a second flag value of the second flag set in a current refresh period.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.