Semiconductor memory device and memory system including the same
US12236997B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 24, 2023 |
| Grant date | Feb 25, 2025 |
| Priority date | — |
| Expiry date | Aug 23, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4096
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a memory cell array including a plurality of memory cell rows, a row hammer management circuit and a control logic circuit. The row hammer management circuit stores counted values in count cells of each of the plurality of memory cell rows as count data based on an active command applied to the control logic circuit at a first time point, and performs an internal read-update-write operation to read the count data from the count cells of a target memory cell row from among the plurality of memory cell rows, to update the count data that was read to obtain updated count data, and to write the updated count data in the count cells of the target memory cell row in response to a precharge command applied at a second time point after a first command that is applied to the control logic circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.