Layout of driving circuit, semiconductor structure and semiconductor memory
US12237030B2 · kind B2 · utility
0Cited by
7References
20Claims
0Family size
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Key dates
| Filing date | Feb 1, 2023 |
| Grant date | Feb 25, 2025 |
| Priority date | — |
| Expiry date | Sep 16, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5602
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A layout of a driving circuit, a semiconductor structure and a semiconductor memory are provided. The layout includes P-type transistors, N-type transistors and four test modules. The four test modules are distributed on both sides of the P-type transistors and the N-type transistors in an upper-lower symmetrical structure, and the P-type transistors and the N-type transistors have an upper-lower structure distribution in the middle of the four test modules.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.