Memory device, memory system having the same, and method of operating the same
US12237048B2 · kind B2 · utility
0Cited by
7References
20Claims
0Family size
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Key dates
| Filing date | Jun 29, 2022 |
| Grant date | Feb 25, 2025 |
| Priority date | — |
| Expiry date | Jan 6, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/01742
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a memory cell array having memory cells connected to wordlines and bitlines, and a clock buffer receiving a clock signal for performing a read operation or a write operation on at least one of the memory cells. The clock buffer includes a plurality of serially connected clock repeaters, and the plurality of clock repeaters have at least one pair of clock repeaters having different imbalanced driving capabilities.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.