Semiconductor package
US12237241B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 12, 2022 |
| Grant date | Feb 25, 2025 |
| Priority date | — |
| Expiry date | Jan 13, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3512
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes: a package substrate; an interposer disposed on the package substrate; a first semiconductor chip mounted on the interposer; a second semiconductor chip mounted on the interposer adjacent to the first semiconductor chip, the second semiconductor chip having an overhang portion that does not overlap the interposer in a vertical direction; a first underfill disposed between the package substrate and the interposer, the first underfill having a first extension portion extending from a side surface of the interposer; a second underfill disposed between the interposer and the second semiconductor chip, the second underfill having a second extension portion extending to an upper surface of the package substrate along at least a portion of the first extension portion of the first underfill, wherein the second extension portion protrudes from the overhang portion contact the upper surface of the package substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.