Delay locked loop and memory
US12237839B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 13, 2023 |
| Grant date | Feb 25, 2025 |
| Priority date | — |
| Expiry date | Oct 10, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/183
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delay locked loop includes a preprocessing module, a first regulable delay line, a second regulable delay line and a first regulation module. The preprocessing module is configured to receive an initial clock signal, preprocess the initial clock signal, and output a first clock signal and a second clock signal. The first regulable delay line is configured to receive the first clock signal, regulate and transmit the first clock signal, and output a first target clock signal. The second regulable delay line is configured to receive the second clock signal, regulate and transmit the second clock signal, and output a second synchronization clock signal. The first regulation module is configured to regulate delay of the second synchronization clock signal based on the first target clock signal, and output a second target clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.