Systems and methods for learning-based high-performance, energy-efficient, and secure on-chip communication design framework
US12238126B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 4, 2021 |
| Grant date | Feb 25, 2025 |
| Priority date | — |
| Expiry date | Nov 17, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05B2219/25198
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods are disclosed for improving on-chip security, while minimizes the latency and cost of security techniques to improve system-level performance and power simultaneously. The framework uses machine learning algorithms, such as an artificial neural network (ANN), for runtime attack detection with higher accuracy. Further, a learning-based attack mitigation method using deep reinforcement learning is disclosed, where the method may be used to isolate the malicious components and to optimize network latency and energy-efficiency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.