Linearity test system, linearity signal providing device, and linearity test method
US12238196B2 · kind B2 · utility
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Key dates
| Filing date | Sep 20, 2021 |
| Grant date | Feb 25, 2025 |
| Priority date | — |
| Expiry date | May 7, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3183
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A linearity test system for a chip, a linearity signal providing device, and a linearity test method for the chip are provided. The linearity test method for the chip includes steps as follows: providing a reference clock signal and a receiver input signal to a chip under test, wherein the reference clock signal and the receiver input signal have a phase difference in time domain; and determining a linearity of a phase interpolator of the chip under test based on a plurality of phase signals of the chip under test corresponding to the reference clock signal and the receiver input signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.