Semiconductor memory device capable of expanding bank capacity adaptively to package size and method of designing the same
US12238925B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | May 5, 2023 |
| Grant date | Feb 25, 2025 |
| Priority date | — |
| Expiry date | Oct 11, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4087
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes n physical banks, each of which is configured to be entirely or partially included in one of a first logic bank or a second logic bank and arranged in a row direction, wherein n is an integer that is greater than or equal to 3, and wherein a proportion of a sum of respective widths of the n physical banks in the row direction to a height of the n physical banks in a column direction is a real number multiple that is not a multiple of 2.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.