Method and apparatus for capture clock control to minimize toggling during testing
US12241931B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 11, 2023 |
| Grant date | Mar 4, 2025 |
| Priority date | — |
| Expiry date | Oct 6, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318575
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method of testing an integrated circuit device includes detecting a number of integrated clock gates (ICGs) in the device. Each ICG can stop clock propagation in a respective branch of a clock tree of the device. For each detected ICG, an ICG fanout (a number of digital inputs that the output of each ICG can feed) is compared with a threshold number of registers. When the ICG fanout is greater than the threshold number, it is determined whether a function-enable path of an existing ICG is timing-critical. When the function-enable path of the existing ICG is timing-critical, an additional ICG and a test point are inserted into the device as a clock input to the existing ICG. When the function-enable path of the existing ICG is not timing-critical, a test point and an AND-gate may be inserted in that function-enable path.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.