Array substrate and display panel
US12242161B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Apr 27, 2022 |
| Grant date | Mar 4, 2025 |
| Priority date | — |
| Expiry date | Apr 27, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/481
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
The present application provides an array substrate and a display panel. The array substrate includes a gate of a thin film transistor; a first electrode of the transistor, including a first body and a first end; a second electrode of the transistor, including a second body and a second end; orthographic projections of the first body and the second body being located in an orthographic projection of the gate, orthographic projections of at least partial area of the first end and at least partial area of the second end not overlapping with the orthographic projection of the gate, an orthographic projections of the first end and the second end being both located on the same side of the orthographic projection of the gate; in a first direction, an average distance from the first end to the second end is greater than that from the first body to the second body.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.