Memory sparing to improve chip reliability
US12242338B2 · kind B2 · utility
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2References
16Claims
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Key dates
| Filing date | May 26, 2023 |
| Grant date | Mar 4, 2025 |
| Priority date | — |
| Expiry date | Jul 11, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7201
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The mapping of system memory addresses to physical memory addresses is modeled as a two dimensional mapping array. Each element of the mapping array is assigned a system memory address and a physical memory address to which the system memory address is mapped. The mapping array is arranged to facilitate designation of a portion of the physical memory addresses as spareable physical memory addresses that are employed when there is a memory failure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.