Memory error processing method and apparatus
US12242339B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2021 |
| Grant date | Mar 4, 2025 |
| Priority date | — |
| Expiry date | Aug 26, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2069
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a memory error processing method, a processor of a computer apparatus obtains from a basic input/output system (BIOS) first error description information that describes a type of a first error that has occurred in a first memory page. Based on the first error description information, the processing device identifies the type of the first error to be a first type, wherein an error of the first type is a corrected error and is not a mirror scrub success error. The processor then determines that a number of errors of the first type that occurred in the first memory page has reached a threshold. In response to the determining, the processing device takes the first memory page offline.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.