Memory cell array unit
US12242340B2 · kind B2 · utility
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2References
7Claims
0Family size
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Key dates
| Filing date | Oct 7, 2021 |
| Grant date | Mar 4, 2025 |
| Priority date | — |
| Expiry date | Oct 21, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N99/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell array unit according to an embodiment of the present disclosure includes a microcontroller that performs reading and writing from and into a memory cell array using n-bit allocation memory cells on the basis of read/write control from a memory controller. When a defect is found in one of the n-bit allocation memory cells, the microcontroller writes n−1-bit write data excluding data of a least significant bit among n-bit write data into n−1-bit allocation memory cells excluding the defective allocation memory cell among the n-bit allocation memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.