Graphics processor
US12243119B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 28, 2022 |
| Grant date | Mar 4, 2025 |
| Priority date | — |
| Expiry date | Apr 8, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T2200/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A graphics processor including geometry and fragment processing logic, and a memory manager arranged to allocate and deallocate memory for use to hold tile data. The memory manager tracks which memory regions are allocated to hold tile data of which subdivisions (e.g. macrotiles) of the render area. Once the fragment processing logic has finished processing the tile data of a subdivision, it sends an identifier of that subdivision to the memory manager for deallocation. The processor further comprises a blocking circuit enabling the fragment processing logic to start processing tile data of a second task while the memory manager is still deallocating some of the memory regions allocated to the subdivisions of a first task; by preventing identifiers of subdivisions of the second task being passed to the memory manager until it has completed deallocating the memory regions allocated to the first task.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.