Gate driving circuit and display device
US12243499B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 1, 2023 |
| Grant date | Mar 4, 2025 |
| Priority date | — |
| Expiry date | Nov 1, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2320/0295
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides a gate driving circuit and a display device. An nth stage circuit among a plurality of stage circuits included in a gate driving circuit according to embodiments of the disclosure may include a scan output buffer circuit configured to output a scan signal according to voltages of a Q node and a Qb node, a control circuit including a plurality of transistors to control the voltages of the Q node and the Qb node, the plurality of transistors including a first Q node discharge transistor turned on or off by the voltage of the Qb node to control connection between the Q node and a low-potential voltage node, and a body bias circuit configured to supply a body bias voltage to a body of a first Q node discharge transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.