Control circuit of power factor improvement circuit and semiconductor integrated circuit device
US12244223B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 5, 2023 |
| Grant date | Mar 4, 2025 |
| Priority date | — |
| Expiry date | May 5, 2043 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02B70/10
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides a power factor improvement circuit with a DC/DC converter including an arithmetic circuit. A first voltage having a full-wave rectified waveform is received by an input voltage detection terminal of the power factor improvement circuit. A second voltage is generated by amplifying an error between a first detection voltage and a reference voltage according to an output voltage of the DC/DC converter. A third voltage is generated by multiplying the first voltage by the second voltage. The arithmetic circuit adds an offset voltage to a third voltage to generate a fourth voltage. A comparator is configured to compare a second detection voltage with the fourth voltage. A drive circuit is configured to turn on/off drive of the switching transistor according to an output of the comparator. When the second detection voltage is higher than the fourth voltage, the switching transistor is turned off.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.