Semiconductor structure integrating logic element and memory element

US12245418B1 · kind B1 · utility

Inventor

• Chun-Ming Lin · Dashulong, TW

Key dates

• Filing date: Oct 30, 2024
• Grant date: Mar 4, 2025
• Expiry date: Oct 30, 2044

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/664

Abstract

A semiconductor structure integrating a logic element and a memory element includes a substrate, a logic element and a memory element. The substrate has a first region and a second region laterally adjacent to the first region. The logic element is disposed in the first region of the substrate, and the memory element is disposed in the second region of the substrate. The logic element includes multiple transistors. The memory element includes an upper electrode, a lower electrode, and a dielectric layer disposed between the upper electrode and the lower electrode. The lower electrode includes a first metal layer, and a first copper-phosphorus alloy layer extending along a contour of the first metal layer to surround the first metal layer. The upper electrode includes a second metal layer, and a second copper-phosphorus alloy layer extending along a contour of the second metal layer to surround the second metal layer.