Layered series-connected power supply circuit and data processing device for supplying power to computing chips connected in series from bottommost layer to highest layer
US12248349B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 13, 2021 |
| Grant date | Mar 11, 2025 |
| Priority date | — |
| Expiry date | Nov 3, 2041 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure is directed to a series-connected power supply circuit and a data processing device. The series-connected power supply circuit comprises: at least two layers of to-be-powered chips (A1, A2, . . . , Am) connected in series between a first power supply end (A) and a second power supply end (B), with a highest-layer to-be-powered chip (Am) in the at least two layers of to-be-powered chips (A1, A2, . . . , Am) connected to the first power supply end (A), and a bottommost-layer to-be-powered chip (A1) in the at least two layers of to-be-powered chips (A1, A2, . . . , Am) connected to the second power supply end (B); and each layer of auxiliary power supply units (B1, B2, . . . , Bm), which is respectively connected to each layer of the to-be-powered chips (A1, A2, . . . , Am), wherein the first power supply end (A) is configured to receive a reference voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.